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A NEW DOUBLE-RANK REALIZATION OF SEQUENTIAL MACHINES = NOUVELLE REALISATION A DOUBLES RANGS DE MACHINES SEQUENTIELLESGAITANIS N; HALATSIS C.1978; I.E.E.E. TRANS. COMPUTERS; USA; DA. 1978; VOL. 27; NO 12; PP. 1137-1143; BIBL. 9 REF.Article

A NEW DESIGN METHOD FOR M-OUT-OF-N TSC CHECKERSGAITANIS N; HALATSIS C.1983; IEEE TRANSACTIONS ON COMPUTERS; ISSN 0018-9340; USA; DA. 1983; VOL. 32; NO 3; PP. 273-283; BIBL. 9 REF.Article

ON THE MINIMIZATION OF THE CONTROL STORE IN MICROPROGRAMMED COMPUTERSHALATSIS C; GAITANIS N.1978; I.E.E.E. TRANS. COMPUTERS; USA; DA. 1978; VOL. 27; NO 12; PP. 1189-1192; BIBL. 5 REF.Article

NEGATIVE FAILSAFE SEQUENTIAL CIRCUITSGAITANIS N; HALATSIS C.1980; ELECTRON. LETTERS; GBR; DA. 1980; VOL. 16; NO 16; PP. 615-617; BIBL. 8 REF.Article

MU P APPLICATION: 6800 REPLACES MINICOMPUTERS AND CONTROLS ELEVATORSHALATSIS C; SOKOS A.1979; DIGIT. DESIGN; USA; DA. 1979; VOL. 9; NO 4; PP. 62-66; (4 P.)Article

IRREDUNDANT NORMAL FORMS AND MINIMAL DEPENDENCE SETS OF A BOOLEAN FUNCTIONHALATSIS C; GAITANIS N.1978; I.E.E.E. TRANS. COMPUTERS; USA; DA. 1978; VOL. 27; NO 11; PP. 1064-1068; BIBL. 12 REF.Article

FLOATING-POINT AND MULTIBIT-INCREMENT DIGITAL-DIFFERENTIAL-ANALYSER STRUCTURESPHILOKYPROU G; HALATSIS C.1972; ELECTRON. LETTERS; G.B.; DA. 1972; VOL. 8; NO 21; PP. 531-532; BIBL. 4 REF.Serial Issue

MICROPROCESSOR-CONTROLLED ELEVATORHALATSIS C; SOKOS A.1978; ELECTRON. ENGNG; GBR; DA. 1978; VOL. 50; NO 613; PP. 81-89; (5 P.)Article

PSEUDOCHAINING IN HASH TABLEHALATSIS C; PHILOKYPROU G.1978; COMMUNIC. A.C.M.; USA; DA. 1978; VOL. 21; NO 7; PP. 554-557; BIBL. 7 REF.Article

ERROR-CORRECTING CODES IN BINARY-CODED RADIX-R ARITHMETICHALATSIS C; GAITANIS N; SIGALA M et al.1983; IEEE TRANSACTIONS ON COMPUTERS; ISSN 0018-9340; USA; DA. 1983; VOL. 32; NO 3; PP. 326-328; BIBL. 10 REF.Article

ON THE PROBLEM OF FINDING D, T, R, AND J TYPE PARTITION PAIRS OF A SEQUENTIAL MACHINE.PHILOKYPROU G; HALATSIS C; GAITANIS N et al.1977; I.E.E.E. TRANS. COMPUTERS; U.S.A.; DA. 1977; VOL. 26; NO 3; PP. 294-297; BIBL. 7 REF.Article

DESIGNING BLOCK-STRUCTURED BUBBLE-UP BUFFERS.HALATSIS C; PHILOKYPROU G; MARITSAS D et al.1976; ELECTRON. ENGNG; G.B.; DA. 1976; VOL. 48; NO 578; PP. 45-48; BIBL. 5 REF.Article

FAIL-SAFE COUNTERSGAITANIS N; HALATSIS C; SIGALA M et al.1979; DIGIT. PROCESS; CHE; DA. 1979; VOL. 5; NO 1-2; PP. 43-57; ABS. FRE/GER; BIBL. 8 REF.Article

POLYLINEAR DECOMPOSITION OF SYNCHRONOUS SEQUENTIAL MACHINES = DECOMPOSITION POLYLINEAIRE DES MACHINES SEQUENTIELLES SYNCHRONESHALATSIS C; SIGALA M; PHILOKYPROU G et al.1978; I.E.E.E. TRANS. COMPUTERS; USA; DA. 1978; VOL. 27; NO 12; PP. 1144-1152; BIBL. 7 REF.Article

MICROCOMPUTER IMPLEMENTED RANDOM AND KEY STREAM GENERATING MECHANISMSARVILLIAS AC; MARITSAS DG; HALATSIS C et al.1980; EUROMICRO J.; NLD; DA. 1980; VOL. 6; NO 3; PP. 161-167; BIBL. 4 REF.Article

ANALYSIS OF BLOCK-ORGANIZED BUFFERS FOR POISSON INPUT AND PERIODIC BLOCK OUTPUT.HALATSIS C; MARITSAS D; PHIKOKYPROU G et al.1974; INTERNATION. J. SYST. SCI.; G.B.; DA. 1974; VOL. 5; NO 1; PP. 29-40; BIBL. 9 REF.Article

Microprocessor-based far infrared spectrophotometerHATZOPOULOS, A; HALATSIS, C.Review of scientific instruments. 1984, Vol 55, Num 9, pp 1498-1502, issn 0034-6748Article

ARCHITECTURAL CONSIDERATIONS FOR A MICROPROGRAMMABLE EMULATING ENGINE USING BIT-SLICESHALATSIS C; VAN DAM A; JOOSTEN J et al.1980; ANNUAL SYMPOSIUM ON COMPUTER ARCHITECTURE. 7/1980/LA BAULE; USA; NEW YORK: IEEE; DA. 1980; PP. 278-291; BIBL. 9 REF.Conference Paper

Performance of circuit-switched interconnection networks under nonuniform traffic patternsPOMBORTSIS, A; HALATSIS, C.The Journal of systems and software. 1993, Vol 20, Num 2, pp 189-201, issn 0164-1212Article

Analysis of a modified model for synchronous multiprocessor systemsPOMBORTSIS, A; HALATSIS, C.The Journal of systems and software. 1986, Vol 6, Num 4, pp 361-365, issn 0164-1212Article

Behaviour of circuit-switched multistage networks in presence of memory hot spotPOMBORTSIS, A; HALATSIS, C.Electronics Letters. 1989, Vol 25, Num 13, pp 833-834, issn 0013-5194, 2 p.Article

Performance analysis of interconnection networks of a mofified model for synchronous multiprocessorsPOMBORTSIS, A; HALATSIS, C.Electronics Letters. 1986, Vol 22, Num 4, pp 222-224, issn 0013-5194Article

Efficient modular design of m-out-of-2m TSC checkers, for m=2K-1, K>2EFSTATHIOU, C; HALATSIS, C.Electronics Letters. 1985, Vol 21, Num 23, pp 1083-1084, issn 0013-5194Article

Near-perfect codes for binary-coded radix-r arithmetic unitsGAITANIS, N; HALATSIS, C.IEEE transactions on computers. 1983, Vol 32, Num 5, pp 494-497, issn 0018-9340Article

L-machine: a low-cost personal sequential inference machineVLAHAVAS, J; HALATSIS, C.The Journal of systems and software. 1989, Vol 9, Num 3, pp 209-223, issn 0164-1212Article

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